This invention relates to memory elements, and more particularly, to memory element reading circuitry with leakage current compensation.
Integrated circuits often contain volatile memory elements. Typical volatile memory elements are based on cross-coupled inverters (latches) and are used to store data. Each memory element can store a single bit of data. In integrated circuits such as programmable logic device integrated circuits, volatile memory elements are used to store configuration data.
Memory elements are typically arranged in arrays. Data may be loaded into the memory elements of the array and may be read from the memory elements of the array using data lines. There is typically a data line associated with each row or column of the array.
An output latch at the end of each data line may be used in conveying data signals from the data line to circuitry outside of the memory array. The output latch may include a pair of cross-coupled inverters. One of the cross-coupled inverters may be directed outwards and may drive data from the data line onto an output terminal. The other of the cross-coupled inverters may be directed inwards and may feed the output terminal signal back onto the data line. During read operations, a memory element of interest is addressed using an address signal. The data bit on this memory elements is driven onto the data line and, through the outwardly-directed inverter of the output latch, is driven in inverted form onto the output terminal.
Each data line is typically connected to numerous memory elements, each of which potentially has a non-negligible amount of associated leakage current. A p-channel metal-oxide-semiconductor pull-up transistor in the inwardly-directed inverter of the output latch can be used to help pull the data line high when the signal on the output terminal is low. Proper operation of the memory array circuitry depends on the ability to select a suitable strength for this pull-up transistor. If the pull-up transistor is made too strong, it may not be possible to drive a stored “zero” data bit from an addressed memory element onto the data line. If the pull-up transistor is made too weak, leakage currents from the memory elements that are associated with the data line may overwhelm the pull-up transistor and pull the data line to ground. In this situation, it may not be possible to drive a stored “one” data bit from an addressed memory element onto the data line.
As integrated circuit technology advances, it is becoming increasingly desirable to reduce transistor linewidths and to reduce the power supply voltages used on a circuit. These advances may help to improve the power consumption on an integrated circuit while allowing for increases in transistor density. Nevertheless, integrated circuits with reduced power supply voltages are increasingly susceptible to manufacturing and operating parameter variations. Conventional memory array arrangements may provide insufficient margin to accommodate these variations when implemented using modern integrated circuit technology. For example, it may be difficult or impossible to appropriately size pull-up transistors in memory array output latches using conventional designs.
It would therefore be desirable to be able to provide improved memory element reading circuitry for integrated circuits.